Explain the difference between Verilog Task and Verilog Function?
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Posted On: Feb 22, 2018
Difference between Verilog Task and Verilog Function
| Verilog Task | Verilog Function |
|---|---|
| A task can contain time-controlling statements. | A function shall execute in one simulation time unit. |
| A task can enable functions as well as other tasks. | A function is not able to enable a task. |
| A task can be with or without an input argument | A function must have at least one input as an argument. |
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